Memory cell arrays comprising charge-trapping memory cells having memory transistors that can be programmed by channel hot electrons (CHE) and can be erased by hot holes, for example, in particular comprising planar SONOS memory cells or NROM memory cells (U.S. Pat. No. 5,768,192, U.S. Pat. No. 6,011,725 and International Patent No. WO 99/60631) having planar MOS transistors and an oxide-nitride-oxide storage layer sequence as gate dielectric require voltages of 4 to 5 volts for programming and erasing, which may be regarded as a disadvantage. Moreover, the memory cells can only be miniaturized more extensively if they are not arranged in one plane one beside the other but rather at the walls of trenches, which are etched out at the top side of a semiconductor body.
A multiplicity of such trenches run at a distance from and parallel to one another and thus form a kind of comb structure at the surface of the semiconductor body. The channels of the memory transistors are arranged vertically at the trench walls. The source and drain regions are arranged at the top side of the semiconductor body in a manner adjoining the trenches and in the trench bottoms. The source/drain regions are connected to bit lines. The gate electrodes of the memory transistors are arranged in the trenches and are connected to word lines arranged transversely with respect to the bit lines on the top side of the memory cell array.
The gate dielectric is formed at the walls of the trenches by a storage layer sequence for which an oxide-nitride-oxide layer sequence is customarily used. In this case, the nitride layer is provided as the actual storage layer in which, during the programming of the cell, electrons are trapped between the boundary layers made of oxide (trapping).
A virtual ground array comprising NROM cells is customarily connected to word lines that run above the source/drain regions and cross with buried bit lines. The transistor current, therefore, flows parallel to the word lines.
This results in various difficulties. The memory transistors cannot be optimized by a more precise setting of the source/drain dopings (LDD, pocket implantation). The word lines have a small cross section, so that fast access to the memory contents is not possible owing to the low electrical conductivity caused as a result of the small cross section. Since the isolation between adjacent channel regions is preferably effected by a channel stop implantation, dopants diffusing into the channel region can bring about a non-uniform current distribution in the channel together with a significant occurrence of the narrow width effect.
U.S. Pat. No. 6,469,935 B2 describes an array architecture nonvolatile memory and its operation methods. In this array, there are a plurality of first connection regions connecting together a first cluster of four memory cells within a square and comprising source/drain regions of the cell transistors, and a plurality of second connection regions connecting together a second cluster of four memory cells within a square and comprising source/drain regions of the cell transistors, each pair of first and second clusters comprising one cell in common. The operation method makes use of control gates connected to control lines that run in parallel with the word lines and are arranged on both sides adjacent to the word lines.
U.S. Pat. No. 5,679,591 describes a method for fabricating a contactless semiconductor memory with bit lines on the top side, in the case of which bit line strips are in each case arranged between the word line stacks and interconnect the source/drain regions of the successive memory transistors along the word lines. The channel regions are oriented transversely with respect to the word lines and are mutually isolated from one another by trench isolations.